With the size of Complementary Metal-Oxide-Semiconductor (CMOS) device being continuously scaled down, the influences of the short channel effect and the charge carrier mobility deterioration effect in the device are increasingly serious. With respect to the development of the silicon-based CMOS technology, the requirements for the ability of suppressing the short channel effect and the ability of improving the charge carrier mobility in the device become more and more urgent.
When the feature sizes of devices enter into sub-100 nm regime, the short channel effect of the device is deteriorated, so that the method for obtaining better performance by further reducing the size of the devices becomes extremely difficult. In order to relieve the pressure resulted from the reduction of the device size, stress is introduced into a channel by adopting strained-silicon technology so as to improve the charge carrier mobility in the channel and the performance of a transistor device, which has become a method widely adopted and indispensable in the engineering of microelectronic fabrication. With the stress being introduced into a channel region of a transistor by means of the device structure, material, and process design, the lattice structure of crystals is varied, and thus leads to the variation of the carrier mobility. Under appropriate stress, the carrier mobility may be improved. For example, the tensile stress in the channel direction improves the electron mobility, and the compressive stress in the channel direction improves the hole mobility.